As a switching device with the ability of maintaining the state of on or off when the power source is switched off (non-volatility), prior to this invention exists firstly an antifuse device, secondly EEPROM (Electrically Erazable and Programmable Read Only Memory), thirdly an electron device which can control the conductance by utilizing a mixed conductor, which is a sort of solid electrolyte, fourthly a PMC (Programmable Metallization Cell), fifthly a PCRAM (Programmable Conductor Random Access Memory), and sixthly a PCM (Phase Change Memory).
The antifuse device as the first prior art is a switching device that has two electrical states, on and off, and can irreversibly transit from off to on state by using either an electrical or physical method. The antifuse device is usually composed between two interconnection layers, and is electrically connected these two layers. It is programmed (transition from off to on state) by biasing a high voltage selectively between these interconnection layers. This on state is maintained after the voltage source is disconnected (see U.S. Pat. Nos. 5,070,384, 5,171,715, 5,387,812, and 5,543,656, and Japanese publication No. JP 08-78532A).
The EEPROM as the second prior art consists of a floating gate electrode that is sandwiched between the control gate electrode of a transistor and its channel layer. The transistor is turned on or off by being charged or discharged electrically via the floating gate electrode. This charge or discharge is conducted by a tunneling current through an oxide film where electrons are injecting into or discharging from the floating gate electrode. Since the floating gate electrode is surrounded by insulating film, the stored charge is not lost after the power source is switched off and the non-volatility is attained (see U.S. Pat. Nos. 4,203,158, and 4,366,555).
The antifuse device and EEPROM are now used for FPGA (Field Programmable Gate Array). The FPGA is a device in which hardware configuration can be changed for each application. A user can wire logic circuit blocks by switching devices, and various hardware configurations can be attained by different wiring positions. This FPGA has, compared with ASIC (Application Specified Integrated Circuit), various merits such as being general commodity and hence can be manufactured with low cost and short TAT (Turn Around Time), and hence its market scale is rapidly expanding.
The electron device as the third prior art is a switching device utilizing silver sulfide that is a silver ion conductive solid electrolyte (see Japanese publication No. JP 2002-76325A).
The solid electrolyte is a material in which ions can move around freely in a solid. So far many materials showing cations and anions conductivity have been found. In case that the solid electrolyte contains a metal, metal ions move in a solid and transport an electric current when an electric field is applied. Furthermore, a mixed conductor that is a sort of a solid electrolyte is capable of the electron conduction in addition to the ionic conduction.
FIG. 18 shows the structure of an electron device disclosed in Japanese publication No. JP 2002-76325A. As shown in the figure, silver sulfide 61 is formed on a semiconductor substrate 63 by sulphidizing the surface of silver wire, and it is set close to platinum wire 62 as a counter electrode. Since the gap between silver sulfide 61 and the platinum wire 62 is small, when a positive voltage on silver sulfide 61 and a negative voltage on platinum wire 62 are applied by a power source 67, silver ions 64 in silver sulfide 61 are deposited on the surface as silver atom, a silver bridge 65 is formed over the gap to platinum, and a point contact is formed. In this case, current between silver sulfide 61 and platinum wire 62 does not flow while the bridge 65 is not formed, but begins to flow when the bridge 65 is formed. Formation and disappearance of the bridge 65, that is, on and off occur at about 0.2V and at high speed, shorter than microsecond.
The electron device PMC as the fourth prior art, for example, a two terminal switch device using chalcogenide (see U.S. Pat. No. 5,761,115 (FIG. 1 and FIG. 4B)).
FIG. 19 is a cross-sectional view showing the structure of the electron device as the fourth prior art mentioned above. The PMC 70 device comprises an ion conductive layer 72 on a substrate 71 between a cathode 73 and an anode 74. When a voltage is applied between the cathode 73 and the anode 74, a dendrite 75 grows along the outer side surface of the ion conductive layer 72 from the cathode 73 toward the anode 74, which forms a current path resulting in switching action. The figure shows dendrite 75 growing along the surface of ion conductive layer 72. The ion conductive layer 72 consists of As2S3—Ag (arsenic trisulfide-silver) that is a solid electrolyte material like the silver sulfide mentioned above. The resistance change of this electron device is, for example, 2.65 MΩ in the off state and 2.1 MΩ in the on state.
The PCRAM as the fifth prior art is a two terminal switching device utilizing silver germanium-selenide that is a silver ion conductive solid electrolyte (see U.S. Pat. No. 6,348,365B1 (FIG. 6)).
FIG. 20 is a cross-sectional view showing the structure of PCRAM as the fifth prior art mentioned above. PCRAM 80 comprises an insulation material 81, a conductive material 82, and a dielectric material 83 on a semiconductor substrate 87, with a recess structure (groove structure) in part of the dielectric material 83. In the recess structure an ion conductive material 86 and a metal 84 are provided, and an electrode 85 is provided on both the metal material 84 and the dielectric materials 83. The ion conductive material 86 is solid electrolyte material like silver sulfide mentioned above. When a voltage is applied between the electrode 85 and the conductive material 82, the current path, called a dendrite, is formed on the surface of the ion conductive material 86, and the electrode 85 and the conductive material 82 are electrically connected. When the opposite voltage is applied, the dendrite disappears, and the electrode 85 and the conductive material 82 are electrically isolated.
The PCM as the sixth prior art utilizes the conductivity change that results from the phase change between a crystal and an amorphous phases in a chalcogenide semiconductor. The phase change of a chalcogenide semiconductor is the binary phase change between the crystal and the amorphous states which can be induced by heating and cooling it or by applying either one of two kinds of pulses with a varying pulse width and pulse amplitude. This phase change depends not on the applied voltage polarity but on the pulse width, amplitude, and so on, of the voltage pulse (see U.S. Pat. Application Publication No. U.S. 2002/0081804-A1).
The antifuse device as the first prior art is the switching device mainly used for FPGA, and is characterized by its short signal delay owing to the small resistance in the “on” state. However, this device cannot be re-programmed, therefore in the case of FPGA programming, such requests as debugging or program modification during operation cannot be met. On the other hand, the EEPROM as the second prior art is capable of re-programming, but its wiring is complex because of the three terminal structure and its integration density is low. The “on” resistance of this device is as large as several kΩ, as it is limited by the MOS transistor resistance. The electron device as the third prior art requires a gap between the mixed conductor and the counter electrode. Making a gap requires additional process that in turn lowers the yield.
As for the electron devices as the fourth and fifth prir arts, since the dendrite, which acts as the current path, is formed on the surface around solid electrolyte, it is questionable whether a high reliability is expected over a long period of time use.
Furthermore, for the electron device as the fifth prir art, the ion conductive material 86 is buried in the recess structure formed in the dielectric material 83. In order to bury the ion conductive material 86 into the recess structure, it is necessary to planarlize the surface by using CMP (Chemical Mechanical Polishing) method. Furthermore, in order to bury the metallic material 84 into the dielectric material 78 a recess has to be formed by using either a dry or wet etching method, which increases the complexity of the manufacturing process and hence increases the cost.
Furthermore, as for the electron device as the sixth prior art, since the crystal and amorphous phases are formed by heating chalcogenide semiconductor using two pulses of different wave shapes and changing the cooling time in effect, the control of pulse shape is complex and the resistance change is small.